The present invention generally relates to semiconductor memory devices and more particularly to a semiconductor memory device that has a capability for controlled activation of sense amplifiers. More particularly, the present invention relates to a semiconductor memory device such as a random access memory (DRAM) having a construction for selective activation of sense amplifiers. However, the present invention is by no means limited to DRAMs but is applicable also to static random access memories (SRAMs) or flash memories.
FIG.1 shows the schematical construction of a typical DRAM having a storage capacity of 64 Mbits in a plan view.
Referring to FIG. 1, the memory device includes a chip body 1 that carries thereon a plurality of row decoders 2-5 for decoding row address data, a plurality of memory cell arrays 6-13 each having a storage capacity of 8 Mbits, and a plurality of driver arrays 14-21 for activating sense amplifiers by producing drive signals.
FIG.2 shows schematically the construction of the memory cell arrays 6 and 7, wherein the hexadecimal numbers attached to the reference numerals indicate the location of the element designated by the reference numeral in the memory cell array.
Referring to FIG.2, each memory cell array includes a number of memory cell blocks 22A.sub.O -22A.sub.F, 22B.sub.O -22B.sub.F, 23A.sub.O -23A.sub.F and 23B.sub.O -23B.sub.F, each having a size of 256 kbits and including therein memory cells arranged in 256 rows and 1024 columns. In addition, the memory cell array includes rows of sense amplifiers 24.sub.0 -24.sub.F and 25.sub.0 -25.sub.F.
FIG.3 shows a part of the memory cell array 6, wherein the elements shown in FIG.3 include hexadecimal indices indicative of the location of the element in the memory cell array 6.
Referring to FIG.3, the memory cell array 6 includes memory cell segments 26.sub.000 -26.sub.0FF and 26.sub.100 -26.sub.1FF each having a predetermined size, and there are provided a number of drive lines 27.sub.00 -27.sub.0F and 27.sub.10 27.sub.1F extending vertically in FIG.3 for carrying a drive signal NSA that is supplied to n-MOS transistors forming the sense amplifiers. Similarly, there are provided a number of drive lines 28.sub.00 -28.sub.0F and 28.sub.10 -28.sub.1F for carrying a drive signal PSA to be supplied to p-MOS transistors that form the sense amplifiers together with the p-MOS transistors.
In addition, the construction of FIG.3 includes drivers 29.sub.00 -29.sub.0F for producing drive signals NSA.sub.00, PSA.sub.00, . . . NSA.sub.0F and PSA.sub.0F for driving a first group of the sense amplifiers located in the upper-half part of the memory cell array 6, as well as other drivers 29.sub.10 -29.sub.1F that produce drive signals NSA.sub.10, PSA.sub.10, NSA.sub.1F and PSA.sub.1F for driving the other group of the sense amplifiers located in the lower-half part of the memory cell array 6.
The drive signals NSA.sub.00 -NSA.sub.0F are supplied to the drive lines 27.sub.00 27.sub.0F via trunks 30.sub.00 -30.sub.0F, while the drive signals NSA.sub.10 -NSA.sub.1F are supplied to the drive lines 27.sub.10 -27.sub.1F via trunks 30.sub.10 -30.sub.1F.
Similarly, there are provided trunks 31.sub.00 -31.sub.0F for supplying the drive signals PSA.sub.00 -PSA.sub.0F to the drive lines 28.sub.00 -28.sub.0F and trunks 31.sub.10 -31.sub.1F for supplying the drive signals PSA.sub.1O -PSA.sub.1F to the drive lines 28.sub.10 -28.sub.1F.
It should be noted that the trunks 30.sub.00 -30.sub.0F, 30.sub.10 -30.sub.1F, 31.sub.00 14 31.sub.0F and 31.sub.10 -31.sub.1F are provided at an upper level of the drive lines 27.sub.00 -27.sub.0F, 27.sub.10 -27.sub.1F, 28.sub.00 -28.sub.0F and 28.sub.10 -281F on the chip 1.
FIG.4 shows a circuit diagram of the DRAM of FIG.1 corresponding to the part of the memory cell segment 26.sub.000 and the driver 29.sub.00, wherein it will be noted that there are provided word lines WL.sub.0 . . . WL.sub.n, and WL.sub.n+1 . . . WL.sub.2n in correspondence to the memory cell segment 26.sub.000 for selecting a memory cell. Similarly, there are provided complementary bit pairs BL.sub.0, /BL.sub.0, . . . BL.sub.m and/BL.sub.m for carrying out read/write operation of data to and from the selected memory cell.
In FIG.4, there are provided a number of memory cells 32.sub.00 . . . 32.sub.0m, 32.sub.n0 . . . 32.sub.nm, 32.sub.(n+1)0 . . . 32.sub.(n+l)m, and 32.sub.(2n)0 . . . 32.sub.(2n) m disposed in a row and column formation, wherein the memory cells are selected by selection circuits 33 and 34. Further, there are provided sense amplifiers 35.sub.0 and 35.sub.m for amplifying the information read out from the selected memory cell.
In order to select a bit line pair, column gates 36.sub.0 . . . 36.sub.m are provided, and data buses DB and /DB, provided commonly to the bit line pairs BL.sub.0, /BL.sub.0, . . . BL.sub.m and/BL.sub.m, are selected in response to control signals CL.sub.0 . . . CL.sub.m that activates the corresponding column gates 36.sub.0 . . . 36.sub.m.
The sense amplifier such as the amplifier 29.sub.00 includes p-MOS transistors 38 and 39 as well as n-MOS transistors 40 and 41. The sense amplifier is thereby supplied with a precharge voltage VPR (VPR=1/2 Vcc) and is controlled in response to complementary activation signals.phi. and/.phi. as well as complementary reset signals R and/R.
When reading data, a memory cell block is selected from the cell array groups 6-9 and 10-13 shown in FIG.1. For example, when data is to be read out from the cell array group formed of the memory cell arrays 6-9, a memory cell block such as the blocks 22A.sub.k, 22A.sub.k+1, 23A or 23A.sub.k+1 or a block such as 22B.sub.k, 22B.sub.k+1, 23B and 23B.sub.k +1 is selected, wherein k is an even integer.
In this example, therefore, drive signals NSA.sub.0k and PSA.sub.0k are supplied from a driver 29.sub.0k via drive lines 27.sub.0k and 28.sub.0k respectively. Similarly, drive signals NSA.sub.0(k+1) and PSA.sub.0(k+1) are supplied from a driver 29.sub.0(k+1) via drive lines 27.sub.0(k+1) and 28.sub.0(k+1) respectively. Similarly, drive signals NSA.sub.1k and PSA.sub.1k are supplied from a driver 29.sub.1k via drive lines 27.sub.1k and 28.sub.1k respectively, drive signals NSA.sub.1(k+1) and PSA.sub.1(k+1) are supplied from a driver 29.sub.1(k+1) via drive lines 27.sub.1(k+1) and 28.sub.1(k+1) respectively.
In DRAM or semiconductor memory devices in general, it is necessary to drive the entire sense amplifiers substantially at the same drive voltage in order to secure a reliable reading operation. In order to achieve this, it is necessary to suppress the parasitic resistance of the drive lines of the sense amplifiers as small as possible.
On the other hand, recent semiconductor memory devices having a miniaturized device pattern uses a correspondingly miniaturized conductor pattern for the drive lines 27 or 28 of the sense amplifiers. Thereby, it has been difficult to supply a sufficient drive current to the sense amplifiers, and there has been a problem in the reliable reading operation of the semiconductor memory device.
As a solution to the foregoing problem, the DRAM of FIG.1 employs a construction wherein a memory cell array such as the memory cell array 6 is divided into two regions, one including a memory cell segment 26.sub.000 -26.sub.0FF and the other including a memory cell segment 26.sub.100 -26.sub.1FF, both of the memory cell segments being arranged in a 16.times.16 formation, such that the drive lines 27 and 28 are divided into two line segments, such as a segment 27.sub.00 and a segment 27.sub.10 or a segment 28.sub.00 and a segment 28.sub.10. Thereby, the length of the drive lines is decreased by one-half and the effect of the parasitic resistance of the drive lines is reduced.
Even with the foregoing construction, however, the reduction of the parasitic resistance of the drive lines is not satisfactory. Thus, there is a desire to divide the memory cell array into eight regions to reduce the parasitic resistance further.
In order to realize such a construction wherein the number of trunks is increased, however, it is necessary to secure a sufficient width for the individual conductor patterns of the trunks 30.sub.00 -30.sub.0F, 30.sub.10 -30.sub.1F, 31.sub.00 -31.sub.0F and 31.sub.10 -31.sub.1F such that a sufficient drive current is supplied to the sense amplifiers. However, such an increased width of the conductor patterns contradicts with the requirement of increased number of the trunks, and because of this reason, it has been conventionally difficult to divide the drive lines 27 or 28 into eight segments. The foregoing problem of increase of the parasitic resistance becomes a major problem in the memory devices having a storage capacity exceeding 64 Mbits such as a DRAM having a 256 Mbit capacity.
In the DRAM or other semiconductor memory devices having such a segmented construction of the memory cell array as shown in FIG.3, it should be noted that one has to selectively activate the drivers 29.sub.00 -29.sub.0F and 29.sub.10 -29.sub.1F. As such a selective activation requires supplying of various control signals to each of the drivers, the area of the chip that is occupied by the conductor patter for carrying such control signals increases substantially, particularly when the number of the drive line segments is increased for reducing the parasitic resistance of the drive lines.
Thereby, there arises a problem that the area that is used for the memory cell array is decreased.